As process technology shrinks the feature sizes of transistors, integrated circuit operating voltages must be reduced every process generation to limit the tolerant electric fields across the terminals of the transistors. In certain semiconductor manufacturing processes, voltages in excess of 2.0 V across the gate-drain junctions of the transistors pose a potential for gate oxide breakdown, thus negatively impacting the reliability and quality of the devices produced through these processes.
FIG. 1 is a cross-sectional representation of the composition of a typical n-channel MOSFET device. An n-channel MOSFET is composed of two n+ regions 108 embedded within a p-substrate 110. Gate 102 is separated from the substrate 110 by oxide layer 112. Channel 114 is a conducting n-type region which is formed when the gate 102 is brought positive with respect to the source 106 and substrate 110. Reducing the transistor size affects not only the dimension of the transistor, but the performance characteristics of the transistor, as well. For example, reducing the lateral dimension of a transistor pushes the drain 104 and source 106 closer to one another. This effectively reduces the amount of time required for electrons to flow from the drain to the source. Making the oxide layer 112 thinner can also enhance the performance of the transistor. A thinner oxide layer creates a stronger effective electric field and reduces the threshold voltage, V.sub.t, thus increasing the effect of the gate voltage on electron flow.
Shrinking a transistor, however, makes it less tolerant to high voltage differentials between its terminals. For example, if the drain and source are too close together, "pun-ch through" may occur. Pun-ch through results from the flow of electrons between the drain and source even if no channel is created. Similarly, if the oxide layer 112 is made too thin, an excessive gate voltage could cause oxide breakdown which results in a short circuit between the three terminals. Even if breakdown does not occur, it is possible for transistor performance to degrade over time through oxide charging effects. Thus, shrinking a transistor lowers the tolerance of the transistor with regard to gate voltages. Consequently, if the gate of the transistor is normally connected to an internal voltage supply, the supply voltage level must be reduced below the maximum tolerable terminal voltage of the transistor.
New integrated circuit devices often incorporate transistors produced with the latest process technology since they feature faster performance and lower power supply requirements. However, in order to maintain compatibility with previous generation products, it is often necessary to continue to support higher voltages at the input/output pins of these devices. For example, older generation computer circuits utilizing CMOS or TTL devices may require supply voltages from 2.5 V to 5 V. These voltage requirements may thus force the input/output transistors produced by a given semiconductor production process to be tolerant of voltages higher than are supported by that process technology.
One method of interfacing low voltage integrated circuit (IC) devices to higher voltage circuits is to provide protection transistors as buffers on the input and output stages of the integrated circuit. These buffers use the internal supply voltage (V.sub.cc) of the IC to bias the gates of the input and output transistors to a value which is lower than the external voltage level. Thus, as long as the internal voltage supply operates properly, the devices within the core and the input/output stage operate safely. If, however, the internal voltage supply either fails to turn on, or turns on after the higher external voltage is present on the input/output terminals of the device, the voltage reducing buffers can be rendered inoperable. This internal voltage supply failure is referred to herein as a "power sequencing problem" and can result in potentially irreversible damage to the remaining circuits within the device.
It is therefore an intended advantage of the present invention to provide a circuit which protects the input/output stage of a low voltage integrated circuit device from a failure of the internal voltage supply or a difference in the power-up sequencing of supply voltage levels.